1. Field of the Invention
This invention generally relates to manipulating the hierarchy of a large transistor level design, and more specifically, to manipulating the hierarchy of such designs to enable application of transistor level timing to the designs.
2. Prior Art
In a VLSI chip design consisting of many millions of transistors, hierarchy is employed to divide the design into some number of sub-designs, where the amount of information in the sub-design (being smaller than the amount of information in the complete design) is in some way more tractable. For instance, a design is divided hierarchically to meet software-tool constraints, or such that responsibility for each sub-design in the hierarchy can be parceled out to separate engineers.
An important part of the VLSI chip design is determining the operating frequency of the chip being designed, both for marketing reasons and design reasons. For example, if an engineer knows the slowest path (the path that determines the operating frequency), then that path can be fixed, making the chip go faster.
In the past, timing has been done at three levels:
A. transistor level circuit simulation: slow and of limited capacity, B. event based simulation: slow, low accuracy, high capacity, C. static timing analysis: fast, low accuracy, high capacity.
Recent advances have provided a new class of timers, referred to as xe2x80x9ctransistor-level-timersxe2x80x9d (TLT). TLT is an order of magnitude slower than static timing analysis, but orders of magnitude faster than transistor level circuit simulation. TLT""s capacity is an order of magnitude less than static timing analysis, but orders of magnitude more than transistor level circuit simulation. TLT""s accuracy is not as good as transistor level circuit simulation, but much better than static timing analysis. Designers want to apply TLT to large designs, but have been limited by capacity constraints.
An object of the present invention is to provide an improved technique for manipulating the hierarchy of a large transistor level design.
Another object of this invention is to manipulate the hierarchy of a large transistor level design so as to enable application of transistor level timing to the design
Addressing this problem is complicated by a number of facts. In particular, a transistor design usually comes with a pre-defined hierarchy; and for a number of reasons, this hierarchy is not suitable for direct application of TLT.
1. In TLT, partition boundaries introduce inaccuracy. The TLT design wants to have as small a number of partitions as possible, given other constraints, such as the maximum number of transistors in a partition that TLT can handle. Transistor level VLSI designs usually have a large number of very small partitions.
2. At the same time, chip designers want the hierarchy used in TLT to be as close as possible to the original design hierarchy, because that is what they""re familiar with.
3. TLT times transistor structures called Channel Connected Components (CCC). It is a requirement that the TLT hierarchy have no cross hierarchy boundary CCCs. The original design hierarchy often has many cross hierarchy boundary CCCs.
Thus, and with reference to FIG. 1, in order to properly rearrange the schematic, three requirements need to be addressed: (1) no cross-hierarchy boundary CCCs, (2) the partition size needs to be acceptable, and (3) preserving the original hierarchy.
These three requirements conflict with each other, and as a result an optimum compromise solution must be found in order to run TLT as accurately and quickly as possible, and to give designers information in a form that they can recognize.
The above-discussed problem is addressed, in accordance with the present invention, by providing a method and system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level. The method comprises the steps of identifying a desired number of blocks for the second hierarchical level, representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary, and identifying transistor networks that extend across block boundaries. The method further comprises the steps of assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and re-assigning some of the transistors among the blocks to reduce the maximum number of transistors in any one block.
Preferably, the transistors are re-assigned among the blocks by identifying partitions for groups of transistors; and then reassigning transistors on the basis of those partitions. For example, the transistors may be partitioned on the basis of functionality, by name, to minimize connectivity, or to duplicate pre-existing hierarchy.
With reference to FIG. 2, the preferred partition procedure of this invention produces several advantages. Capacity constraint problems are reduced, in that one tool cannot do the entire chip; and accuracy is increased because the larger the partition, the more accurate the timing. Also, run time balancing is improved due to the fact that the partitions can be timed in parallel.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.